SpaceWire IP Core (PicoSkyFT)
SkyLabs d.o.o.
Rad-hard-by-design, fault tolerant 8/16-bit embedded processor IP core (PicoSkyFT) for SoC integration.
Technical specifications
- Product code
- SKY-9001
- Architecture
- Harvard enhanced RISC pipelined architecture, ~1 MIPS/MHz
- Instruction set
- PicoSky ISA with 140 instructions, high code density
- Operating modes
- Supervisor, User, Debug, Sleep, Reset
- Radiation hardening
- Radiation hardened by design; all memories EDAC protected (Multiple SEC-DED)
- Register protection
- Parity protected supervisor and user register files with diagnostic bypass
- Traps controller
- FDIR policy fully user-definable per fault cause
- Program memory models
- Compact (8 kB), Small (64 kB), Medium (128 kB), Large (8 MB)
- Data memory models
- Normal (64 kB) or Extended (16 MB)
- Interrupt controller
- Configurable, customisable number of prioritised interrupt vectors
- Debug facilities
- Debug Support Unit (DSU), trace buffer, PicoSkyLINK programmer/debugger interface
About
PicoSkyFT is designed for embedded processing functions within an SoC, providing another layer of abstraction to tackle complexity and adequately respond to rapidly changing needs, and securing development and verification efforts. Rad-hard by design, small in size, low power and configurable, its architectural features are optimised for hard, real-time processing, making this processor core suitable for aerospace and other safety-critical applications. PicoSkyFT is a high-performance Fault Tolerant 8/16-bit embedded processor based on a Harvard-enhanced RISC pipelined architecture, designed to provide a solution that fits between overloaded FPGAs and hugely complex microprocessors. The processor provides a rich and powerful proprietary PicoSky ISA with 16-bit operation codes and single-cycle execution on most instructions, delivering throughput of 1 MIPS per MHz. The SEE-tolerant design is achieved by several error mitigation techniques and an incorporated fault detection, isolation and recovery policy to increase reliability. The core is customisable to suit various memory models.
Documentation
No public datasheet yet — request the datasheet / ICD from the supplier.
